The present invention relates to integrated circuits, and, more particularly, to a system for performing electrical characterization of integrated circuits.
Integrated circuits are widely used in computer systems for performing various functions. Such circuits also include internal circuits that work in tandem. Examples of such circuits are processors, logic gates, flip-flops, latches, system buses, and so forth. These circuits are often referred to as functional circuits. The functional circuits are driven by a clock. Depending on the system requirements, different functional circuits may require different clock signals for their operation e.g., an integrated circuit may include one set of functional circuits that operates in a first clock domain and another set of functional circuits that operates in a second clock domain. Such integrated circuits are referred to as asynchronous integrated circuits. The data transferred through these functional circuits across multiple clock domains is also asynchronous. The asynchronous operation of such integrated circuits makes accurate testing difficult.
An integrated circuit undergoes rigorous testing before it is deemed fit for operation. One such type of testing involves checking the input/output (I/O) interface signal timing with respect to a reference signal, such as a clock or strobe signal. The I/O interface signals are required to meet certain setup and hold time specifications with respect to the corresponding reference clock or strobe signal. Such testing is referred to as electrical characterization of I/O interfaces. In electrical characterization, Automatic Test Equipment (ATE) is used. For electrical characterization of output interfaces, test patterns are used to configure functional circuits to output actual data at the I/O interface in defined cycles, and the ATE is configured to expect the same data on the I/O interfaces in same cycles. If the output data captured by the ATE does not match the expected test data, the integrated circuit is considered faulty. Similarly for electrical characterization of input interfaces, test patterns are used to configure functional circuits and I/O interfaces in input mode. The ATE is configured to drive defined data patterns on the input pads in defined cycles with required setup and hold margins for a corresponding reference clock signal.
Electrical characterization of asynchronous integrated circuits is much more difficult. Due to the asynchronous nature of the data transfers, the times at which outputs appear at the I/O interfaces are not deterministic. Many factors and process variations are known to introduce this variance, such as temperature, voltage, process variation and the like. Changes in these factors may impact the data transfer timings and lead to cycle-shifted outputs at the I/O interfaces. The ATE would consider such cycle-shifted outputs as erroneous and thus the device would fail electrical characterization.
Electrical characterization techniques LAO perform use the functional circuit path during testing, where an ATE will drive test data on the desired I/O interface and issue clock signals to shift the test data across multiple functional circuits within the integrated circuit. The ATE captures the test data output at an I/O interface and compares it with expected data. However, this kind of functional electrical characterization has many disadvantages. Firstly, the data is transferred through the entire functional circuit path, which takes time and thus increases test time. Secondly, the data has to be driven across multiple clock domains before it is captured at the I/O interface. Further, the ATE must have significant post-processing capabilities and special logic to handle the indeterministic output at the I/O interfaces. Such ATEs are costly and lead to an increase in the test costs.
It would be advantageous to have a test system with that can perform electrical characterization of asynchronous integrated circuit interfaces relatively quickly. It also would be advantageous to reduce the test pattern size and memory requirements of test systems.